Research Interests

I am interested in efficient hardware design methodologies for making intelligent services more affordable and accessible. I have worked on abstraction-based hardware design space exploration, and I am currently studying how design abstractions can be translated into practical hardware implementation. Going forward, I hope to develop design flows for emerging workloads that efficiently explore hardware design spaces and realize the resulting designs as verifiable hardware systems.

Education

Ulsan National Institute of Science and Technology (UNIST)

2021 – 2027 (expected)

Bachelor of Engineering in Electrical and Electronic Engineering

GPA: 4.22 / 4.30 (through Fall 2025)

Honors & Awards

Unhae Scholarship

UNIST · Merit-based scholarship (KRW 8,000,000)

Feb. 2026

Dean's Award for Academic Excellence

UNIST · EE Department · Department Top 1

Aug. 2025

Dean's Award for Academic Excellence

UNIST · EE Department · Department Top 1

Feb. 2023

New Student Division Award for Academic Excellence

UNIST · Freshman Top 3

Feb. 2022

Publications & Posters

Hyunsung Jeong*, Kyounghun Kang*, Jongeun Lee, and Wanyoung Jung

"B-Flex: Exploration of Broader Flip-Flop Design Space Based on FSM Exhaustive Search"

In Proc. Design Automation Conf. (DAC), 2026

*Equal contribution

Hyunsung Jeong, Sanhtet Aung, and Jongeun Lee

"TBA"

Under review

Selected Projects

High-Level

Low-Level

TBA

Dec. 2025 – Apr. 2026

Researcher, advised by Prof. Jongeun Lee

Details to be announced.

Logic-Aware Validation and Search Methodology for Stateful Hardware Design

Aug. 2025 – Nov. 2025

Researcher, co-advised by Prof. Jongeun Lee and Prof. Wanyoung Jung

Addressed the limited scalability of prior flip-flop exploration methods, which were constrained by incomplete validation and inefficient brute-force FSM search.

Key Highlights

  • Identified incompleteness in prior FSM-based flip-flop validation, showing that test-vector-based checking can miss invalid state-transition behavior
  • Formalized flip-flop correctness as an inductive invariant between circuit-level asynchronous FSMs and logical reference behavior
  • Proposed and implemented a validation-guided search algorithm that prunes invalid candidates early while preserving the complete valid design space
  • Impact: Enabled exhaustive exploration of broader flip-flop mechanisms, discovering hundreds of millions of valid FSMs and synthesized designs that outperform conventional flip-flops

From DSE Abstractions to Synthesizable Hardware Designs

May 2026 – Present

Ongoing Research

Addressing the gap between high-level DSE abstractions and concrete RTL realization in accelerator design.

Key Highlights

  • Goal: Toward design flows where DSE frameworks provide actionable guidance for practical hardware implementation, rather than only ranking abstract design points

Technical Skills

Languages (Advanced)

C++PythonVerilog HDLMATLABLaTeX

Tools (Advanced)

Xilinx Vitis HLSXilinx Vivado Design Suite

Parallelization (Advanced)

CUDAOpenMP

Collaboration

GitOverleafdraw.ioFigma